Verilog/VHDL versus high level functions.

Latency is a matter of pipelining - which is a chain of registers, probably with some logic in between. Registers are inferred from VHDL from a basic template:

process(clk, areset) --remove areset if you dont want an async reset
begin
  if areset = '1' then  --remove if no reset needed
    --async reset
  elsif rising_edge(clk) then
    --do some stuff
  end if;
end process;

So basically you count the number of signal assignments in the chain inside the clocked part of the process to calculate the latency. The less logic (ie gates) between registers and the faster you can run the clock. Remember that control logic (ifs/case etc) will get mapped to gates, so bare this in mind.

I highly recommended you stay away from any HDL until you have a good understanding of the basic logic elements. If you dont, and write some "bad" vhdl - it may simulate just fine but will either be terrible or just not compile at all for the FPGA.