Verilog/VHDL versus high level functions.

All Processes are run in parrallel. You need to think in terms of hardware, not code. The clock will arrive at all processes at the same time, so all code is executed in parrallel.

No, you must check for if areset = '1'. This is a binary system - it will either be 1 or 0. Technically, if reset > '0' then will work, as '1' is defined after '0' in the std_logic definition. But it is not a good idea to use it.

single quotes '' are used to wrap around character types. std_logic is an enumerated type that uses characters for each state (it has 9 states in total, but only 3 are useful for real hardware ('1', '0' and 'Z'). The rest are just for simulation purposes : ('U', 'X', '-', 'H', 'L' and 'W')