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Altera_Forum's avatar
Altera_Forum
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11 years ago

Verilog/VHDL versus high level functions.

Im new to this, coming from audio programming in MSP/Reaktor and lower level assembler. So I have to learn a lot about the FPGA stuff as I go along. But two things came to mind. It was hint...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I mean if the interface node declares a variable that you are going to use in code, and the output does the same.

Wouldnt it be better practice even, to map these directly onto the output rather than creating an intermediate variable?

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What do you mean by interface node? do you mean a port? and variables are specific things in VHDL - they are different from signals.

Did you mean an intermediate signal?