True Dual Port Ram Synthesizes error with two clock signals

Do you have any other VHDL?

The problem is more likely your code being incorrect, or you not doing the interface correctly

What is the Cyclone 3 connected to?

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Do you have any other VHDL?

The problem is more likely your code being incorrect, or you not doing the interface correctly

What is the Cyclone 3 connected to?

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well, for now this is the code i am using,

well may be there be an interfacing problem, but this is such a simple structure now, how could there be any interface problem.

well the cyclone 3 is connected to a RAM and ARM7, over an address and data bus.

also, all these components are on a custom designed pcb, i.e. fpga, ram, arm7, variable power supplies..etc..

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Obviously, the "microcontroller stops working" issue can't be solved without tri-stating the data output to the bus. This would require in the first place a bidirectional (inout) port declaration, and secondly additional logic setting the output to (others => 'Z') when unselected. The tri-state operation isn't part of the RAM MegaFunction. On write, the cs would be decoded into WE signal, on read, it can be ignored by the RAM, only the bus tri-state matters.

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well, ok, this works, i have added the tristate as you suggested, and the conflict with Arm has been removed now. but i still have to make sure that the dpram(in fpga) works when it is being enabled by the micro-controller (arm).

Hello Again,

well, i have got some very strange results, but before that i would like to mention few things, i had a problem with configuring my fpga with my designed core, and form every forum and altera support i was said that there is a problem with my vhdl core design. but, last night, i discovered something new and strange,

what i did is i moved to one of the Altera Quartus tools " Chip Planner", and then i randomly select some regions (LogicLock Regions) and forced the Fitter to add my logic in that region, and with a series of hit and trials at certain point the whole logic starts to work, but with some errors, i would also like to mention that in my current design i am also using a True Dual Port Ram MegaCore, and now certain addresses of this MegaCore are not accessible to read and write. and these unaccessible addresses are randomly spread over the region.

so now the question could be that is there a way to test the silicon region of this FPGA, or can i test all the cells inside FPGA that are they dead or alive or working/not-working ??

Regards

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Im guessing you have some unregistered read or write ports, and so you are causing timing problems as you move it around the FPGA, but these timing problems will be different for different parts of the FPGA because of different routing delays.

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first apology for a mistake, actually i can read those bad memory locations, but can not write, or what i write is not written so those registers are readable only or so... for instance, the register addressed 0x00 is always 0xcc , no matter what i write on it its always this 0xcc.

okay about the timing problems, yes that might be true, but i just made a small test, and what i did, i simply remove the True DualPort Ram form rest of the core, and configured the fpga with this design. and all the registers of the RAM work properly, then i moved the exact same working design to some other location / region of FPGA and, the DualPorted ram stopped working.

so now the reasons.

could it be that the silicon of the FPGA is damaged?? or

could it be because of the VCC/GND connections of the FPGA?? or

some kind of interference inside FPGA??

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could it be that the silicon of the FPGA is damaged?? or

could it be because of the VCC/GND connections of the FPGA?? or

some kind of interference inside FPGA??

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My first instinct would be that it is none of these, and something to do with your tests and logic set up. If any of these were the case, I dont think anything would work. Please post some of the code you are using.