True Dual Port Ram Synthesizes error with two clock signals

Hello Again,

well, i have got some very strange results, but before that i would like to mention few things, i had a problem with configuring my fpga with my designed core, and form every forum and altera support i was said that there is a problem with my vhdl core design. but, last night, i discovered something new and strange,

what i did is i moved to one of the Altera Quartus tools " Chip Planner", and then i randomly select some regions (LogicLock Regions) and forced the Fitter to add my logic in that region, and with a series of hit and trials at certain point the whole logic starts to work, but with some errors, i would also like to mention that in my current design i am also using a True Dual Port Ram MegaCore, and now certain addresses of this MegaCore are not accessible to read and write. and these unaccessible addresses are randomly spread over the region.

so now the question could be that is there a way to test the silicon region of this FPGA, or can i test all the cells inside FPGA that are they dead or alive or working/not-working ??

Regards