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Altera_Forum's avatar
Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Im guessing you have some unregistered read or write ports, and so you are causing timing problems as you move it around the FPGA, but these timing problems will be different for different parts of the FPGA because of different routing delays.