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Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

FvM has outlined the problem. Because you need chip selects you need to implement tri-state buffers on the IO. the CS signals control the tri-states and the we goes into the memory. The memory has no tri-state drivers of its own, so you have to write them yourself.