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Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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could it be that the silicon of the FPGA is damaged?? or

could it be because of the VCC/GND connections of the FPGA?? or

some kind of interference inside FPGA??

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My first instinct would be that it is none of these, and something to do with your tests and logic set up. If any of these were the case, I dont think anything would work. Please post some of the code you are using.