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Altera_Forum's avatar
Altera_Forum
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15 years ago

True Dual Port Ram Synthesizes error with two clock signals

Hello, well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error Error: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

okay, may be you are rite, but, what if the logic is correct, i mentioned in my previous post, i used a MegaCore (true DualPorted Ram) generated by MegaWizard in Quartus, its no more my vhdl code, and now this MegaCore, works in some regions of FPGA and it wont works in the other. so i think the logic is correct. may be we should think about some hardware issue then??