Altera_Forum
Honored Contributor
Honored ContributorTotal execution time and propagation delay
hi,
How to calculate total execution time and propagation delay for VHDL files under Quartus II? Thank youForum Discussion
21 Replies
Altera_ForumWhat clock speed have you specified in your SDC file? without one, Timequest will check the timing at 1000Mhz (which is much faster than is realistically acheiveable). But it will report the fmax for the circuit (which is the fastest clock speed you could run the design at).
- Altera_Forum--- Quote Start --- What clock speed have you specified in your SDC file? without one, Timequest will check the timing at 1000Mhz (which is much faster than is realistically acheiveable). But it will report the fmax for the circuit (which is the fastest clock speed you could run the design at). --- Quote End --- Thank you Trichky, Using your informations i was able solve problems. Now i have a synchronous adder without errors. So, how to calculate the total execution time of this adder by using "TimeQuest Timing Analyser" ? Best Regards,
- Altera_Forum
You dont.
You count the number of registers in the pipeline and that is your latency (probably what you mean by ttotal execution time). - Altera_Forum--- Quote Start --- You dont. You count the number of registers in the pipeline and that is your latency (probably what you mean by ttotal execution time). --- Quote End --- I mean by "total execution time", the time required to execute the circuit(Addr) in the fpga.
- Altera_Forum
A circuit does not "exectue" inside an FPGA - it always exists, and is always running. It is a circuit, not a piece of software.
- Altera_Forum--- Quote Start --- A circuit does not "exectue" inside an FPGA - it always exists, and is always running. It is a circuit, not a piece of software. --- Quote End --- If a circuit does not "exectue" inside an FPGA, why it has a Fmax? Can we not consider T=1/Fmax a minimum execution time of a circuit?
- Altera_Forum
The Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline.
FPGAs contain circuits, not programs. - Altera_Forum--- Quote Start --- The Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline. FPGAs contain circuits, not programs. --- Quote End --- Forme, the time required to calculate the result using inputs values is "the total execution time", and i want calculate it. If the latency is the same as the "total execution time", how can we calculate it?
- Altera_Forum
You just work out how many registers are in the pipeline. You can easily do that from the code/simualtion.
- Altera_Forum--- Quote Start --- You just work out how many registers are in the pipeline. You can easily do that from the code/simualtion. --- Quote End --- I am not accustomed to do that(I am a beginner). Have you a tutorials that deal this topic?
