Total execution time and propagation delay

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The Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline.

FPGAs contain circuits, not programs.

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Forme, the time required to calculate the result using inputs values is "the total execution time", and i want calculate it. If the latency is the same as the "total execution time", how can we calculate it?