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Altera_Forum
Honored Contributor
11 years agoTotal execution time and propagation delay
hi, How to calculate total execution time and propagation delay for VHDL files under Quartus II? Thank you
Altera_Forum
Honored Contributor
10 years agoWhat clock speed have you specified in your SDC file? without one, Timequest will check the timing at 1000Mhz (which is much faster than is realistically acheiveable). But it will report the fmax for the circuit (which is the fastest clock speed you could run the design at).