Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThe Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline.
FPGAs contain circuits, not programs.