Timing contrain

Question

Hi,

By using Megafunction altsyncram, is there any method to know the timing value for the following before it violated?

Megafunction -> M9k, 30ns period

Reference -> http://subversion.assembla.com/svn/micro_core/referencje/altera/ug_ram.pdf

1) tWC - the maximum write cycle time ( what is the value)

2) tWE - the write enable interval time

3) the time write enable need to be valid after the rising clk

4) the time data and address need to be valid after the write enable

thanks in advance for the help,

regards

tan

altera_forum · Answer

You are talking about FPGA OnChip memory.

These memory blocks can handle up to fmax that is possible depending upon the target fpga device you are using. Quartus knows the timing requirements for the specified device. for example if a specific fpga can run at a internal fmax of 200MHz then the onchip memory can also run at 200MHz. you need to look at the datasheet of your fpga

so you do not need to look at these memories as if they were off chip devices were you need to obey tWC and tWE.

altera_forum · Answer

thanks for your reply MSchmitt,

If I were using Aria II EP2AGX125EF35I5ES, when i look at the datasheet -> http://www.altera.com/literature/hb/arria-ii-gx/aiigx_5v3.pdf

I could not find any information for the above. Am I looking for the wrong data sheet?

altera_forum · Answer

sorry i think you didn't understand what i tried to explain.

the timing parameters for FPGA OnChip memory is well known and obeyed (if possible) by quartus. you don't have to think about timing parameters for on chip memory as if it is an external memory where you must obey the tWC and tWE parameters. so you won't find these parameters, at least i haven't seen them and havn't searched for them

the onchip memory runs as fast as the fmax of the fpga is. that means you can read and write up to fmax. If fmax is 400MHz then you can write at 400MHz and each memory cycle is 1 clock ....

altera_forum · Answer

Thanks again, now I get what you had means.

Btw, does that apply to address setup time as well? The address lines are in active full clk cycle before the data out. We need a further data on address setup time.

By trying to interface some of this RAM with PCI back end bus. And to cut down the number of clock cycles required, had tried to connect the backend bus address signal to the RAM without register. However there is combinational address going on, selecting the particular block ram to pay attention to.

.

So, does the address setup time would be same as above as well?

Many thanks for answering

altera_forum · Answer

so you want to make the internal memory accessible for external access like PCI ?

if you have registers at the input to syncronize the external signals to the internal clock and registers at the output, the internal memory timing shouldn't worry you as quartus will obey the timing of the registers and internal memories as long as it is possible. otherwise you will get the timing warning information.

if you external signals are not related to a clock that is a input to your internal logic, i am quit unshure what the best practise would be. sorry i did had this problem yet.

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Timing contrain

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