Timing contrain

There are some subtle things about these ram blocks, one is that the input and output REGS are optional. The address input is LATCHED whether or not there is an input reg. So without the reg the hold time is for the latch function. Your address in does not have to be held steady for the entire cycle, just long enough to get latched. The documentation says that the output reg only delays the output 1 cycle, so it seems like the reg options are to be used in pipelined designs. The documentation button menu on Megawizard will generate sample waveforms and other info about the other options as well. Violating setup/hold times on the input can corrupt the memory contents, so be very sure to sync up external signals in order to drive the array.