Timing contrain

Thanks again, now I get what you had means.

Btw, does that apply to address setup time as well? The address lines are in active full clk cycle before the data out. We need a further data on address setup time.

By trying to interface some of this RAM with PCI back end bus. And to cut down the number of clock cycles required, had tried to connect the backend bus address signal to the RAM without register. However there is combinational address going on, selecting the particular block ram to pay attention to.

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So, does the address setup time would be same as above as well?

Many thanks for answering