so you want to make the internal memory accessible for external access like PCI ?
if you have registers at the input to syncronize the external signals to the internal clock and registers at the output, the internal memory timing shouldn't worry you as quartus will obey the timing of the registers and internal memories as long as it is possible. otherwise you will get the timing warning information.
if you external signals are not related to a clock that is a input to your internal logic, i am quit unshure what the best practise would be. sorry i did had this problem yet.