Timing contrain

You are talking about FPGA OnChip memory.

These memory blocks can handle up to fmax that is possible depending upon the target fpga device you are using. Quartus knows the timing requirements for the specified device. for example if a specific fpga can run at a internal fmax of 200MHz then the onchip memory can also run at 200MHz. you need to look at the datasheet of your fpga

so you do not need to look at these memories as if they were off chip devices were you need to obey tWC and tWE.