Honored Contributor
Honored Contributorsorry i think you didn't understand what i tried to explain.
the timing parameters for FPGA OnChip memory is well known and obeyed (if possible) by quartus. you don't have to think about timing parameters for on chip memory as if it is an external memory where you must obey the tWC and tWE parameters. so you won't find these parameters, at least i haven't seen them and havn't searched for them the onchip memory runs as fast as the fmax of the fpga is. that means you can read and write up to fmax. If fmax is 400MHz then you can write at 400MHz and each memory cycle is 1 clock ....
