system design using cyclone II

Hi Dave,

I am now implementing each block unit in quartusII...

several questions:

1. the bit width got me a little confused. My input signal is 16bit, I made the NCO generate 16-bit cosine and sine wave. After mixer, I should have two modulated signals of 32bit width.

Now, I keep the datapath as 32bit, and input each multiplied result into a low-pass FIR filter(developed through megafunction FIR compiler, single rate, coefficients 8bit width). Should I keep the full precision, which is 40bit length, or should I truncate MSB/LSB? from what I learnt before, the ADC has a Vref=+-2V, 16bit, then the signed fractional representation of the sampled data is (3.13), including the signed bit. I guess from NCO, the cosine & sine wave is (1.15), so after mixer it is (4.28). And after FIR the full precision is 42bit, I can keep the first 16bit if my output resolution is 16bit. right?

2. The filtered result will be squared and summed and take the root. How can I decided the bit length then?

Thanks!

Allison

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so, this cosine wave will be sent out of FPGA to modulate the external source current, right? this ensures that the incoming current is locked with the cosine wave from NCO.

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Yes.

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hmm...I am not sure if I get this part.

so if the sampling rate of ADC is 40MSPS. to multiply the input with the cosine& sine, the clk from PLL should be 40Mhz too so the sampling rate of cosine/sine wave from NCO is 40MHz, is that correct?

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You might be able to understand this a little easier if you think about this in terms of samples. Here's some MATLAB code that generates the attached PDF

% Sampling frequency
fs = 40e6;
% Test tone frequency
f0 = 154e3;
% Total sampling time
T = 4/f0; % 4 periods for this example
% Number of samples
Nt = ceil(fs*T);
% Sample index
n = ;
% Time index
t = n/fs;
% NCO output
nco_i  = cos(2*pi*f0*t);
nco_q = sin(2*pi*f0*t);
% Plot I and Q as digital looking waveforms
% (you need to zoom into the figure to see the steps)
figure(1)
hold off
stairs(n, nco_i)
hold on
stairs(n, nco_q, 'r')
axis()

What this plot shows you is the NCO output sampled in time; the samples are spaced 40MHz apart, but the signal they generate is at 154kHz. Is that clearer?

What this example does not show you is that in reality the cosine and sine would also be quantized, eg., rather than defining nco_i = cos(2*pi*f0*t), you would define a signal that can only take on say 8-bit values, i.e., nco_i = round(cos(2*pi*f0*t)*2^7);

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and after LPF, the DC components are cos(phase) and sine(phase), if I wanna get the amplitude, mathematically it is cos^2+sine^2...and should I implement the equation in verilog to get the amplitude?

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Given the outputs of the filters output_i and output_q, the magnitude of the signal is sqrt(output_i^2 + output_q^2). You could calculate these values in Verilog, but I suspect the data update rate you require is probably pretty slow, eg. 1Hz or slower, so you can instead have your logic write the sensor values to RAM (for all the current sensor I and Q output values), and then calculate the sensor position in software.

Cheers,

Dave

Thx Dave!

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3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources.

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so, this cosine wave will be sent out of FPGA to modulate the external source current, right? this ensures that the incoming current is locked with the cosine wave from NCO.

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5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC).

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hmm...I am not sure if I get this part.

so if the sampling rate of ADC is 40MSPS. to multiply the input with the cosine& sine, the clk from PLL should be 40Mhz too so the sampling rate of cosine/sine wave from NCO is 40MHz, is that correct?

and after LPF, the DC components are cos(phase) and sine(phase), if I wanna get the amplitude, mathematically it is cos^2+sine^2...and should I implement the equation in verilog to get the amplitude?

Allison

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It's the current from the PSD sensor that 's been modulated. not the light.

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Ok, thanks for the clarification.

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Now, let's just assume tat we can get a continuous current signal from a certain source. What we are interested is the 154Khz components in the signal.

1. suppose we decide to use a 12bit, 40MSPS ADC to perform the analog-to-digital task (about that, i searched online trying to find information about ADC filter that can suppress frequency components other than 154Khz (for example). but all i found were anti-aliasing filters. it seemed to me like when selecting an ADC, the most important thing was output bits (usually 8bit is more than enough). none of them mentioned the center frequency, like what you said yesterday. could you explain it more to me please?)

2. we need a lock-in amplifier.First I implement a PLL, which produce an output clk of 10Mhz. (btw, can this signal be locked with the 154kHz input???)

3. pass the 10Mhz clk into a NCO, which produces a 154Khz sine wave. (also, there is an optional frequency modulator function in this NCO, I read through the manual sheet, not sure if I goet what they meant. Does it say that through this function, the output sine wave can be locked with an external frequency, say, my original 154Khz signal? if so, why should I still need a PLL? if not, how can I make sure this signal is locked with my 154khz input?)

4. pass the sine wave and the original signal into a mixer.

5. use a LPF that only keeps the DC components.

sorry if I ask too much or some of them dont make sense.... i really want to make sure i understand the whole thing and am able to complete the task.

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You're on the right track. Please open up the attached PDF for a block diagram of the system you would build (or at least its an initial starting point).

1. The system is coherent, i.e., there is a single master clock reference. This could be an oscillator on an FPGA board, or a synthesizer connected to a clock pin via an SMA connector on an FPGA development kit. For example, a 10MHz external reference, or say a 50MHz oscillator on a development kit. The frequency ultimately does not matter, the key here is that the system uses the same reference. For DACs and ADCs, the jitter characteristics of the reference source are critical parameters, but ignore that for now.

2. Lets assume you want to run your DAC and ADC at say 20MHz. The PLL inside the FPGA can take the reference clock and generate multiple 20MHz output signals. Two of the 20MHz signals go to the external DAC and ADC, while the other is used to clock the logic within the FPGA, i.e., your NCO clock frequency is 20MHz.

3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources.

4. The multiple sensor currents are then sampled by multiple copies of the ADC circuit. The ADC samples are multiplied by the in-phase (I) and quadrature (Q, or sinewave) outputs of the NCO. This multiplication demodulates the sensor output, so that the signal of interest lies at DC.

5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC).

What you need to determine is how many bits you need in your ADC, your DAC, and your final output update rate. Alternatively, you can create a MATLAB simulation given the DAC and ADC bit-widths you have access to, quantize signals, add sensor noise, create sampled data, perform the complex-valued multiplication to baseband, filter the result, and see what you get, and then iterate.

Cheers,

Dave

Hi Dave,

I read through the links you gave me yesterday, especially the user manual of NCO. very helpful. Thx!

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It is the light that is being modulated, so that you get modulated currents at the output of your sensor. The reference of the 154kHz modulation source is important, because the sensor processing needs to be synchronous with that source.

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It's the current from the PSD sensor that 's been modulated. not the light. Now, let's just assume tat we can get a continuous current signal from a certain source. What we are interested is the 154Khz components in the signal.

1. suppose we decide to use a 12bit, 40MSPS ADC to perform the analog-to-digital task (about that, i searched online trying to find information about ADC filter that can suppress frequency components other than 154Khz (for example). but all i found were anti-aliasing filters. it seemed to me like when selecting an ADC, the most important thing was output bits (usually 8bit is more than enough). none of them mentioned the center frequency, like what you said yesterday. could you explain it more to me please?)

2. we need a lock-in amplifier.First I implement a PLL, which produce an output clk of 10Mhz. (btw, can this signal be locked with the 154kHz input???)

3. pass the 10Mhz clk into a NCO, which produces a 154Khz sine wave. (also, there is an optional frequency modulator function in this NCO, I read through the manual sheet, not sure if I goet what they meant. Does it say that through this function, the output sine wave can be locked with an external frequency, say, my original 154Khz signal? if so, why should I still need a PLL? if not, how can I make sure this signal is locked with my 154khz input?)

4. pass the sine wave and the original signal into a mixer.

5. use a LPF that only keeps the DC components.

sorry if I ask too much or some of them dont make sense.... i really want to make sure i understand the whole thing and am able to complete the task. Thanks for your help...

Allison

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here is the link for the PSD: "en.wikipedia.org/wiki/Position_sensitive_device"

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Ok, thanks.

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the modulation is performed in the analog domain by somebody else. I dont have a clear mind of what the process is, I can ask him if this is really important to my design.

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It is the light that is being modulated, so that you get modulated currents at the output of your sensor. The reference of the 154kHz modulation source is important, because the sensor processing needs to be synchronous with that source.

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Here is a piece of code I found on line which can transfer a clock into a sine/cosine wave ...

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This is just a very simple NCO.

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so, if the code works, instead of using NCO, I can transform a square wave into a sine wave right? as long as I get a 154Khz clock.

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I doubt the code will work for your application. The Altera NCO component is simple to use. You can also implement sinusoid tables using ROM. At this point, you are still trying to understand all the components in your system will fit together. So for now, just assume you will be using 'something' that creates sine and cosine samples inside the FPGA, and they will correspond to samples of a 154kHz sinusoid. The generic name for that 'something' is NCO (regardless of whether you use the NCO component from Altera).

You now need to determine how the light modulation will be synchronized to your signal processing system, so you can accurately measure the demodulated currents.

Cheers,

Dave

Hi Dave, thanks for clearing up.

here is the link for the PSD: "en.wikipedia.org/wiki/Position_sensitive_device"

the modulation is performed in the analog domain by somebody else. I dont have a clear mind of what the process is, I can ask him if this is really important to my design.

Here is a piece of code I found on line which can transfer a clock into a sine/cosine wave

("edaboard.com/thread39599.html"):

module sine_cos(clk, reset, en, sine, cos);

input clk, reset, en;

output [7:0] sine,cos;

reg [7:0] sine_r, cos_r;

assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};

assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};

always@(posedge clk or negedge reset)

begin

if (!reset) begin

sine_r <= 0;

cos_r <= 120;

end else begin

if (en) begin

sine_r <= sine;

cos_r <= cos;

end

end

end

endmodule // sine_cos

so, if the code works, instead of using NCO, I can transform a square wave into a sine wave right? as long as I get a 154Khz clock.

Allison

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The light doesn't change. The light on the PSD(position sensor detector) will produce two currents I1 and I2 which decide the position of the light (X=(I1+I2)/(I1-I2), this will be performed within FPGA, right now all we want are the currents). After modulation and demodulation we get the interest current signal of 154Khz, combined with noises from other bands.

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This does not make sense. Perhaps you can post a link to the position sensor. You have not clearly described how the light is getting modulated.

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I am quite confused...

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This is ok. You already said this is the first time you have played with hardware.

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from my understanding, a ALT_PLL can generate a sub-frequency clock, i.e. divide the original signal frequency by 1, 2...etc. The output of PLL is a clock that is phase locked to the input signal. I would then transfer this clock into a sine wave

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Here is where you are misunderstanding how things can work in the digital world; you do not transfer the 154kHz sine wave into the analog domain to multiply by the sensor output, you sample the sensor output and take it into the digital domain, and you perform the operations there.

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and then multiply it with the original 154Khz signal and pass the result through a LPF. And all of the above steps will be done within FPGA.

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There is no sine wave from an ALT_PLL, it is a square wave, it is a clock signal. The way you make the digital values that correspond to a stream of samples from a sine wave and a cosine wave is the NCO component clocked by the output of the PLL.

You've got the right idea, you're just a little confused on the implementation.

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what you describe above seems more complex... or maybe I am not following...

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We're saying the same things.

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sorry if I offend anybody here... I was thinking abt using Virtex long time ago but now I am back to Cyclone II.

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I wasn't offended, I don't care what devices you want to use :)

Cheers,

Dave

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This is still not clear. You do not indicate why the light would change at 154kHz. Is the light being 'chopped'. Could you please post a diagram of your setup?

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The light doesn't change. The light on the PSD(position sensor detector) will produce two currents I1 and I2 which decide the position of the light (X=(I1+I2)/(I1-I2), this will be performed within FPGA, right now all we want are the currents). After modulation and demodulation we get the interest current signal of 154Khz, combined with noises from other bands.

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Right. In an FPGA, there would be a PLL, but at a much higher frequency that 154kHz. Inside the FPGA, the PLL would be used to clock a Numerically Controller Oscillator, and the output of that oscillator is a digital sinusoid and cosinusoid. One of those signals can be sent to a digital-to-analog converter (DAC) and filtered to give you a very clean 154kHz reference signal. That signal can be used to drive the sensors in your system.

The sensor output would then be sampled by an analog-to-digital coverter (ADC). The samples would then internally be multiplied by the digital versions of the NCO outputs, i.e., your samples x(t) would be demodulated by the compex-exponential exp(-j*2*pi*fo*t) = cos(2*pi*fo*t) - j*sin(2*pi*f0*t), where f0 = 154kHz, and t = n/fs, where n is the sample index and fs is the sampling frequency. The complex-valued baseband signal would then pass through two digital filters.

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I am quite confused...from my understanding, a ALT_PLL can generate a sub-frequency clock, i.e. divide the original signal frequency by 1, 2...etc. The output of PLL is a clock that is phase locked to the input signal. I would then transfer this clock into a sine wave and then multiply it with the original 154Khz signal and pass the result through a LPF. And all of the above steps will be done within FPGA. what you describe above seems more complex... or maybe I am not following...

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You're on the wrong group if you want help with Xilinx FPGAs. However, the above description would work fine with those parts too.

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sorry if I offend anybody here... I was thinking abt using Virtex long time ago but now I am back to Cyclone II.

Thanks dave.

Allison