Honored Contributor
Honored ContributorThx Dave!
--- Quote Start --- 3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources. --- Quote End --- so, this cosine wave will be sent out of FPGA to modulate the external source current, right? this ensures that the incoming current is locked with the cosine wave from NCO. --- Quote Start --- 5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC). --- Quote End --- hmm...I am not sure if I get this part. so if the sampling rate of ADC is 40MSPS. to multiply the input with the cosine& sine, the clk from PLL should be 40Mhz too so the sampling rate of cosine/sine wave from NCO is 40MHz, is that correct? and after LPF, the DC components are cos(phase) and sine(phase), if I wanna get the amplitude, mathematically it is cos^2+sine^2...and should I implement the equation in verilog to get the amplitude? Allison
