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Altera_Forum's avatar
Altera_Forum
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14 years ago

system design using cyclone II

Hi, I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Dave,

I am now implementing each block unit in quartusII...

several questions:

1. the bit width got me a little confused. My input signal is 16bit, I made the NCO generate 16-bit cosine and sine wave. After mixer, I should have two modulated signals of 32bit width.

Now, I keep the datapath as 32bit, and input each multiplied result into a low-pass FIR filter(developed through megafunction FIR compiler, single rate, coefficients 8bit width). Should I keep the full precision, which is 40bit length, or should I truncate MSB/LSB? from what I learnt before, the ADC has a Vref=+-2V, 16bit, then the signed fractional representation of the sampled data is (3.13), including the signed bit. I guess from NCO, the cosine & sine wave is (1.15), so after mixer it is (4.28). And after FIR the full precision is 42bit, I can keep the first 16bit if my output resolution is 16bit. right?

2. The filtered result will be squared and summed and take the root. How can I decided the bit length then?

Thanks!

Allison