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It's the current from the PSD sensor that 's been modulated. not the light.
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Ok, thanks for the clarification.
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Now, let's just assume tat we can get a continuous current signal from a certain source. What we are interested is the 154Khz components in the signal.
1. suppose we decide to use a 12bit, 40MSPS ADC to perform the analog-to-digital task (about that, i searched online trying to find information about ADC filter that can suppress frequency components other than 154Khz (for example). but all i found were anti-aliasing filters. it seemed to me like when selecting an ADC, the most important thing was output bits (usually 8bit is more than enough). none of them mentioned the center frequency, like what you said yesterday. could you explain it more to me please?)
2. we need a lock-in amplifier.First I implement a PLL, which produce an output clk of 10Mhz. (btw, can this signal be locked with the 154kHz input???)
3. pass the 10Mhz clk into a NCO, which produces a 154Khz sine wave. (also, there is an optional frequency modulator function in this NCO, I read through the manual sheet, not sure if I goet what they meant. Does it say that through this function, the output sine wave can be locked with an external frequency, say, my original 154Khz signal? if so, why should I still need a PLL? if not, how can I make sure this signal is locked with my 154khz input?)
4. pass the sine wave and the original signal into a mixer.
5. use a LPF that only keeps the DC components.
sorry if I ask too much or some of them dont make sense.... i really want to make sure i understand the whole thing and am able to complete the task.
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You're on the right track. Please open up the attached PDF for a block diagram of the system you would build (or at least its an initial starting point).
1. The system is
coherent, i.e., there is a single master clock reference. This could be an oscillator on an FPGA board, or a synthesizer connected to a clock pin via an SMA connector on an FPGA development kit. For example, a 10MHz external reference, or say a 50MHz oscillator on a development kit. The frequency ultimately does not matter, the key here is that the system uses the
same reference. For DACs and ADCs, the jitter characteristics of the reference source are critical parameters, but ignore that for now.
2. Lets assume you want to run your DAC and ADC at say 20MHz. The PLL inside the FPGA can take the reference clock and generate multiple 20MHz output signals. Two of the 20MHz signals go to the external DAC and ADC, while the other is used to clock the logic within the FPGA, i.e., your NCO clock frequency is 20MHz.
3. The numerically controlled oscillator is setup to output a 154kHz sinusoid. The in-phase (I) or cosine wave output of the NCO is sent to the DAC, and that signal is filtered to produce the 154kHz modulation reference for the current sources.
4. The multiple sensor currents are then sampled by multiple copies of the ADC circuit. The ADC samples are multiplied by the in-phase (I) and quadrature (Q, or sinewave) outputs of the NCO. This multiplication demodulates the sensor output, so that the signal of interest lies at DC.
5. The complex-baseband signal is then filtered and decimated down to a sample rate consistent with the signal-to-noise you need from each measurement. For example, if you want the estimates every 1 second, then the output sample rate is 1 second, and the filter preserves the signal with a 1Hz bandwidth (-0.5Hz to 0.5Hz). The complex-valued output can be used to estimate the magnitude and phase of the received signal (sensor output) relative to the transmitted signal (the DAC).
What you need to determine is how many bits you need in your ADC, your DAC, and your final output update rate. Alternatively, you can create a MATLAB simulation given the DAC and ADC bit-widths you have access to, quantize signals, add sensor noise, create sampled data, perform the complex-valued multiplication to baseband, filter the result, and see what you get, and then iterate.
Cheers,
Dave
Honored Contributor
