Altera_Forum
Honored Contributor
Honored Contributorsynchronous data in, synchronous data out issue
I have a single data rate edge-aligned (video) input signal consisting of the following lines:
IMAGER_PCLK (the pixel clock) IMAGER_VSYNC (vertical sync pulse) IMAGER_HSYNC (horizontal sync pulse) IMAGER_DATA(15 downto 0) (16 bits parallel data) My goal is simple, I want to have a process that latches the input signal and then outputs it to the following output lines: ECU_PCLK (the pixel clock) ECU_VSYNC (vertical sync pulse) ECU_HSYNC (horizontal sync pulse) ECU_DATA(15 downto 0) (16 bits parallel data) The latency of data coming in and data coming out of the FPGA is not important, but the relation between the pixel clock and the vsync, hsync and data lines is (needs to be in sync)! Because of the latter, I applied data input and data output constraints based on datasheet values. A snipped of my top level vhdl file given below:
architecture logic of temp_project is
signal imager_pclk_launch : std_logic := '0'; -- frequency of IMAGER_PCLK not shifted
signal imager_pclk_latch : std_logic := '0'; -- frequency is 2xIMAGER_PCLK 90 degrees shifted
-- we use ALTCLKCTRL ip block because IMAGER_PCLK is not connected to dedicated input pin
component imager_pclk_regional is
port
(
inclk : in std_logic := '0';
outclk : out std_logic
);
end component imager_pclk_regional;
-- we use Altera PLL ip block to generate the (source synchronous) latch clock
component imager_pclk_pll is
port
(
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic
);
end component imager_pclk_pll;
begin
u0: component imager_pclk_regional
port map
(
inclk => IMAGER_PCLK,
outclk => imager_pclk_launch
);
u1: component imager_pclk_pll
port map
(
refclk => imager_pclk_launch,
rst => ECU_RESET,
outclk_0 => imager_pclk_latch
);
p1: process (imager_pclk_latch)
begin
if (imager_pclk_latch'event and imager_pclk_latch = '1') then
ECU_PCLK <= IMAGER_PCLK;
ECU_VSYNC <= IMAGER_VSYNC;
ECU_HSYNC <= IMAGER_HSYNC;
ECU_DATA <= IMAGER_DATA;
end if;
end process p1;
end logic;
# **************************************************************# Create Clock# **************************************************************
create_clock -period 13.468
# **************************************************************# Create Generated Clock# **************************************************************
derive_pll_clocks
create_generated_clock -source
# **************************************************************# Set Clock Uncertainty# **************************************************************
derive_clock_uncertainty
# **************************************************************# Set Input Delay# **************************************************************
# IMAGER clock domain (edge-alligned single data rate input signals)
set_input_delay -clock -min -2.500 }]
set_input_delay -clock -max 2.000 }]
# **************************************************************# Set Output Delay# **************************************************************
# ECU clock domain (edge-alligned single data rate input signals)
set_output_delay -clock -min -2.500 }]
set_output_delay -clock -max 2.000 }]
# **************************************************************# Set Maximum Delay# **************************************************************
set_max_delay -from }] -to }] 13.468
# **************************************************************# Set Minimum Delay# **************************************************************
set_min_delay -from }] -to }] 0
