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every time I tried another phase shift I also changed the waveform of the virt_ecu_pclk accordingly
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I'm not sure what you mean by this?
How did you come up with your min/max output delay values? The fact their the same as your input delay values makes me suspicious.
How did you put your sdc file together? What are your 'ECU_XXX' signals driving? What setup and hold times does that device require?
The question of how to correctly specify timing constraints is frequently discussed and frequently described badly. So, I'm not going to risk doing the same by explaining how I think of it.
However, I'll refer you to a document I've previously found useful. The
timequest user guide (
https://www.google.nl/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&ved=0ahukewj9ylzhr7rjahwi7hokhrxbaggq5tuicq&url=http%3a%2f%2fwww.eet.bme.hu%2f~nagyg%2fmikroelektronika%2ftimequest_user_guide.pdf&psig=afqjcnh7w_3m7obncm5ryoefdwvvbzuqfg&ust=1449049374815784) has a section on I/O Timing. It talks you through both input and output delay in a way that, I found, somewhat clearer than many explanations I've read.
I hope that helps.
Cheers,
Alex
Honored Contributor
