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You've generated a gated clock in 'ECU_PCLK'. Gated clocks are not a good idea and often result in, as you've seen, timing problems. However, I'm not sure that's a problem...
So, when 'imager_pclk_latch' is active (high) 'ECU_PCLK' simply latches the state of 'IMAGER_PCLK'? Is that right? In which case 'ECU_PCLK' isn't a clock. However, you've constrained it as one in your generated clocks section.
You've also constrained 'ECU_VSYNC', 'ECU_HSYNC' & 'ECU_DATA' with respect to 'ECU_PCLK'. However, (I'm pretty sure - you've not posted all the code) they're not generated from this clock.
Does your code do what you're expecting - in simulation? What frequency is 'imager_pclk_latch'? I think I need a more complete picture to fully help.
Cheers,
Alex
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Alex, you're right, I believe I do not want ECU_PCLK to be a gated clock, I want it to be a 'real' clock. Actually I want it to be an exact copy of IMAGER_PCLK.
What I really want is that the FPGA at every rising edge +90 degrees of IMAGER_PCLK captures the state of the IMAGER_VSYNC, IMAGER_HSYNC and IMAGER_DATA(15 downto 0) and then set ECU_VSYNC, ECU_HSYNC and ECU_DATA(15 downto 0) accordingly. ECU_PCLK may be derictly derived from IMAGER_PCLK as long as ECU_VSYNC, ECU_HSYNC and ECU_DATA(15 downto 0) lines are edge-aligned with respect to ECU_PCLK. For constraining the edge-alignment I use the values which can be found in the Synopsys Design Constrain file (min=-2.5ns max=2.0ns).
I posted all of the code. It might look useless to just copy the input state from the IMAGER to the ECU output, but I want to add functionality to the process (lets say a shift operation on the data lines) to the process later.
Regards, Richard.
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