synchronous data in, synchronous data out issue

What frequency is 'IMAGER_PCLK'?

Assuming it's appropriate, I suggest you use a PLL, driven by 'IMAGER_PCLK', with two output clocks. The first you will use internally to the FPGA. This will latch the data in to and out of the FPGA. The phase of this clock will need to be appropriately aligned to the data on the incoming 'IMAGER_XXX' signals. The second clock output will drive out of the FPGA. This one you will shift in phase with respect to the data coming out on your latched 'ECU_XXX' signals, to suit the alignment requirements of the device receiving these signals.

If the frequency of 'IMAGER_PCLK' is too low for this (which it may well be, depending on the VGA resolution you're using) then you'll have to use an independent, faster clock to latch the data at 90 degrees. You can then either regenerate 'ECU_PCLK' with logic or, as per your original design, simply drive it directly from 'IMAGER_PCLK'.

Cheers,

Alex