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What frequency is 'IMAGER_PCLK'?
Assuming it's appropriate, I suggest you use a PLL, driven by 'IMAGER_PCLK', with two output clocks. The first you will use internally to the FPGA. This will latch the data in to and out of the FPGA. The phase of this clock will need to be appropriately aligned to the data on the incoming 'IMAGER_XXX' signals. The second clock output will drive out of the FPGA. This one you will shift in phase with respect to the data coming out on your latched 'ECU_XXX' signals, to suit the alignment requirements of the device receiving these signals.
If the frequency of 'IMAGER_PCLK' is too low for this (which it may well be, depending on the VGA resolution you're using) then you'll have to use an independent, faster clock to latch the data at 90 degrees. You can then either regenerate 'ECU_PCLK' with logic or, as per your original design, simply drive it directly from 'IMAGER_PCLK'.
Cheers,
Alex
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Hi Alex,
Thanks a lot for your detailed reply!! Based on your reply I modified my design and Synopsys Design Constraint file. Below is my new VHDL file:
architecture logic of temp_project is
signal imager_pclk_launch : std_logic := '0';
signal imager_pclk_latch : std_logic := '0';
signal ecu_pclk_launch : std_logic := '0';
signal temp_data : std_logic_vector(15 downto 0);
signal temp_vsync : std_logic;
signal temp_hsync : std_logic;
component imager_pclk_regional is
port
(
inclk : in std_logic := '0';
outclk : out std_logic
);
end component imager_pclk_regional;
component imager_pclk_pll is
port
(
refclk : in std_logic := '0';
rst : in std_logic := '0';
outclk_0 : out std_logic;
outclk_1 : out std_logic
);
end component imager_pclk_pll;
begin
u0: component imager_pclk_regional
port map
(
inclk => IMAGER_PCLK,
outclk => imager_pclk_launch
);
u1: component imager_pclk_pll
port map
(
refclk => imager_pclk_launch,
rst => ECU_RESET,
outclk_0 => imager_pclk_latch,
outclk_1 => ecu_pclk_launch
);
p1: process (imager_pclk_latch)
begin
if (imager_pclk_latch'event and imager_pclk_latch = '1') then
temp_vsync <= IMAGER_VSYNC;
temp_hsync <= IMAGER_HSYNC;
temp_data <= IMAGER_DATA;
ECU_VSYNC <= temp_vsync;
ECU_HSYNC <= temp_hsync;
ECU_DATA <= temp_data;
end if;
end process p1;
ECU_PCLK <= ecu_pclk_launch;
end logic;
And my SDC file:
create_clock -name IMAGER_PCLK -period 13.468
create_clock -name virt_imager_pclk -period 13.468
create_clock -name virt_ecu_pclk -period 13.468
create_generated_clock -name ECU_PCLK -source .gpll~PLL_OUTPUT_COUNTER|divclk]
set_input_delay -max -clock virt_imager_pclk 2.000 }]
set_input_delay -min -clock virt_imager_pclk -2.500 }]
set_output_delay -max -clock virt_ecu_pclk 2.000 }]
set_output_delay -min -clock virt_ecu_pclk -2.500 }]
derive_pll_clocks
The frequency of IMAGER_PCLK is 74.25MHz. The clock used for the process, imager_pclk_latch, is 74.25MHz, shifted 180 degrees (with respect to IMAGER_PCLK). All my input timing violations are gone and I concluded that the 180 phase shift is correct. The clock used to drive out of the FPGA, ecu_pclk_launch, is 74.25MHz, not shifted (with respect to IMAGER_PCLK). I tried a few phase shifts (0, 90, 180, 270) for ecu_pclk_launch but I did not succeed to get rid of the output timing violations (every time I tried another phase shift I also changed the waveform of the virt_ecu_pclk accordingly).
My question is whether i'm still doing something wrong? Am I missing something? I there a guideline for trying different phase shifts for launch/latch clocks instead of just trying the brute force way? Is my SDC file complete? Is there a way to reduce the data path lengths or to apply trace length matching within the FPGA?
Thanks in advance! Any help is again much appriciated.
Kind regards, Richard.
Honored Contributor
