synchronous data in, synchronous data out issue

You've generated a gated clock in 'ECU_PCLK'. Gated clocks are not a good idea and often result in, as you've seen, timing problems. However, I'm not sure that's a problem...

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I want to have a process that latches the input signal

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So, when 'imager_pclk_latch' is active (high) 'ECU_PCLK' simply latches the state of 'IMAGER_PCLK'? Is that right? In which case 'ECU_PCLK' isn't a clock. However, you've constrained it as one in your generated clocks section.

You've also constrained 'ECU_VSYNC', 'ECU_HSYNC' & 'ECU_DATA' with respect to 'ECU_PCLK'. However, (I'm pretty sure - you've not posted all the code) they're not generated from this clock.

Does your code do what you're expecting - in simulation? What frequency is 'imager_pclk_latch'? I think I need a more complete picture to fully help.

Cheers,

Alex