Stratix II Configuration Problem

Question

Hi,

We are having some issues configuring a stratix II FPGA. From quartus we can successfully program the flash from Quartus but the FPGA does not always configure correctly when power is applied.

I have attached a schematic of the configuration circuitry. Initially what we are trying to do is configure the FPGA from the EPCS64, but as can be seen in the schematic, another FPGA exists which can also be used to configure it (although this feature will not initially be used or tested). The circuit is laid out so that the stratix II be configured by the Cyclone III, however we have changed the resistors where applicable so that the stratix II FPGA is configured from the EPCS64. (i.e. anywhere an N1 appears, it is actually populated while the neighbouring resistor is not.)

Anyway, to describe the problem we have:

Like I said we can configure the EPCS64 from Quartus without problems, but when power is applied the FPGA does not configure although the CONF_DONE and INIT_DONE pins go high signalling that the FPGA thinks it has configured. We have noticed that while connecting an oscilliscope probe to the CONF_DONE pin to view what is happeneing during configuration, that the FPGA actaully successfully configures. It only seems to configure when the scope is connected to this pin and no other. it seems very strange, I don´t have any ideas as to what is happening.

I initially thought that the other FPGA may be interferring with the configuration process by lowering the CONFIG_N pin, but we have removed resistors R959 and R960 (top right) to ensure that the other FPGA cannot adversely affect configuration.

Also I have noticed that when attempting to configure the device and probing a pin on the FPGA where a clock signal is expected, it does seem that the expected clock signal does exit the FPGA for a brief period. This leads me to believe that the FPGA always gets successfully configured (regardless of wheather the scope is connected to CONF_DONE) but the looses it soon after.

We have the same configuration scheme on a different board but without the other Cyclone III FPGA in place and we don´t have any issues, so we are confident enough that FPGA should configure, but cannot understand what could be the cause of the issue.

Any ideas or suggestions would be most welcome.

Many thanks

altera_forum · Answer

You're schematic isn't attached. Can you attach it?

Clarifications:

1 - So you say that the FPGA seems to always successfully configure when you have a scope probe on the CONF_DONE pin?

2 - Not seeing the schematic, it sounds like your traces are T'd going between the three devices (EPCS64, Stratix II, & Cyclone III). How does the signal integrity look on the Active Serial configuration pins?

3 - Are you using fast active serial or regular active serial? If fast, are you able to try slow?

4 - Have you probed the nConfig pin to see if something is happening there? Is the nConfig pin properly pulled high?

5 - Do you have sufficient grounding to the FPGA?

Can you list any differences you can think of between this design and the other board that works properly?

Jake

altera_forum · Answer

Apologies, file now attached.

As for the clarifications:

1. Yes the FPGA always configures when conf done is probed. (without this it will not configure properly)

2. We havn´t analysed the signal integrity in any great detail, we have only verified that clock and data are as expected, but will look into this in the morning.

3. We are using fast active serial, I dont think we can try slow as the MSEL pins are hardwired apart from one.

4. Yes n_config is pulled high, it seems to be behaving as expected. I initially thought that the other FPGA may have been pulling it low briefly after configuration but this appears not to be the case.

5. At the moment we don´t have any concerns about the grounding, as we followed the recomendations of the datasheet. What type of problems are yout thinking of?

The differences between the boards are the following:

The working board does not have the cyclone III FPGA, but in theory this should not affect operation, as the resistors are configured only to configure the FPGA from the flash. Other than that there are not any other differences that I can think off that could affect configuration, but I´ll post back if I think of anything.

Many thanks for the help

altera_forum · Answer

Well the fact that probing CONF_DONE fixes it is more than odd. We know that CONF_DONE must go high for the device to initialize. Maybe what's happening is noise on the CONF_DONE line is actually causing it to not initialize because you've got the traces running all over.

I have two different experiments to try. I would try number 1 first.

1 - Can you add a capacitor between CONF_DONE and ground? Doesn't have to be too big. maybe 100pF. Though I don't think a larger value could hurt. You could probably actually lay it on top of R418. This would bypass to 3.3 instead of GND but I think either way will work. Try both if one doesn't have any effect.

2 - Try changing change R148 to 1K.

Jake

altera_forum · Answer

My apologies for not posting back on this issue earlier. A few other things came up and I was unable to spend time with this particular issue. We have some other boards which do not exhibit the same problem. So hopefully I will be able to get back to this issue at some stage in the near future and try the suggestions as it does seem like a noise issue.

I´ll post back when I have more information or a solution as it may be of use to someone else at some stage in the future.

Regards

altera_forum · Answer

I'm seeing the same problem with a Cyclone II. Part doesn't configure at power up. Everything checks out and works with the USB Blaster.Sits there retrying continuously. When I tap the DONE line with a scope probe, part springs to life.

Have probed lines; the PCB layout is fine, and the tracks are about 2" long. Good signal integrity at the Cyclone II. Have tried decreasing pullup value on DONE, adding a small capacitor, etc....

-------------revised post ------ FIXED IT--------------

Was originally using EPCS1 with compressed bitstream. Changed to using EPCS4 and uncompressed stream. Worked first time.

Was using Quartus 9.1 build 222, EP2C8Q208C8

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Stratix II Configuration Problem

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