Stratix 10M DIB Module

I'm aware of this document ,

The document leaves many open questions , and does not refer to my questions.

1. The document is talking about system synchronous and not Source synchronous as my case.
2. I didn't find any place that specifies the values of B,C,D Timing values (at the Figure 16) the only timing which was specifies is 2.5ns, it is not written if 2.5ns = EMIB Delay (C values) , or the DIB Latency (B,D values) - or all the values together .
3. My question was to where should I set the input/output delays practically in the SDC, which means to which pins or ports?, it is not written in the document , what is the dib_0 module (in my original question) stand for , is it the "Die B DIB" (at figure 16)? or it is " EMIB+DIE B DIB " ?
4. The importance of item 3 above is to understand if quartos timing analyzer , takes into account the internal routing of dib_0 and derived the clock definition in the input side and add the Routing delay inside the dib_0 module

Thanks

Or

Hi Nurina

1. Clock should be assign to IO – when constraining Source Synchronous interfaces

Look at this training and document and trainings from Intel/Altera.

https://learning.intel.com/Developer/learn/course/168/play/1632:223/constraining-source-synchronous-interfaces

Slide 12,27

https://cdrdv2-public.intel.com/653688/an433.pdf

Section Output Clock Constraints and Input Clock Constraints

2. in System Synchronous – the clock is not transferred with the Data (as in Source Synchronous) – in system Synchronous the clock is transferred to both devices , and should be aligned.
3. where can I find “EMIB Delay=C=Wire Delay of Stratix 10” Values , I search and find nothing about it . which document describes it ?

Searching for EMIB in this document finds nothing.

4. This is not accurate according to “Source Synchronous interface “ - see course and document above .

The output delays of the “Transmitting Device “ is assign to the clock which defined on the output Pin . / Slide 26 ,31 at the training

For the Receiving Device ,you are right, the input delay is according the virtual clock .

5. This is not specific from my implementation this is Module I get when I generated the DIB module .

Hi Nurina.

1. the course / Slides are intel's course how come you dont have access to something that intel publish .

do you have access to this web page :

https://learning.intel.com/Developer/pages/30/all-intel-developer-training

then search :"constraining source synchronous (E-Learning) " and see the course

this course will explain you what is source synchronous and the constraints you need to assign (in general not on DIB specifically )

in addition you can read the document from Intel - attached it now since somehow you can not load it .

I recommend that you do the course first .

2. I'm using ByPass mode of DIB - which means using the DIB as "cable connection" or "replacing cable" , on the DIB you can transfer data , but you can also transfer clock along the data - not as points to the document which is synchronous design . (please watch the course or read what is source synchronous ) . when you transfer clock you have different constraints you need to assign for the input and output delay.

3. Regarding the delay. you are confusing me in your answer .

at your first answer Quotation "The B,C,D timing values from Figure 16 of the above document is as follows. B=D=DIB Latency=2.5ns as mentioned here https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html. EMIB Delay=C=Wire Delay of Stratix 10"

B, D are 2.5 ns DIB Latency what was missing is the EMIB Delay(C , Wire Delay) , and then in your last answer , you sent me to a document which is again talking about DIB Latency and NOT EMIB Delay ...

Quotation from the Document .... "The latency between DIB pins is 2.5 ns."

so Intel Document is missing the finial numbers of DIB Latency and EMIB Delay ... what is the total delay B+C+D = 7.5ns / B+C =5ns or just C=5ns ...

even if working with system Synconus as in the example here: https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html

you need the Value B , C , D which are not described in the document ... (there only vouge number 2.5ns from the document quotation "The latency between DIB pins is 2.5 ns." which is not understood to what parameter it is set .

Hi Nurina,

1. the clock is 13.3Mhz .

2. what is "delay matched clock to each die." ? - send same clock to both dies , but what is the meaning of delay ?

3. Yes I'm trying to have one Clock Source in Die 0 , and transfer the data along with the clock via the DIB to the other Die.

4. even we move to "System Synchronous" (I guess this is what you suggest in "Delay Matched Clock" I'm still looking for the values - see item 3 at my post at "‎01-03-2023 03:54 AM"

BTW it is not written in any document that DIB does not support Clock Transfer via DIB - and now we need to do Huge change in my design - I recommend that Intel will comment about that .

in addition , can you tell if I need to define special parameters when I generate example design ? where can I find the constraints of the 50Mhz you wrote above ?

Or.