Forum Discussion
Occasional ContributorStratix 10M DIB Module
Hi,
I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.
You can start with the values they put for the example design and fine tune it after compilation.
Below are the values used:
- max C=2.65
- min C=-2.65
- max A + max B = 8.25
- min A + min B = 3
- max D + max E = 4.75
- min D + min E = -1.64
Regards,
Nurina
Regular ContributorHello Or,
Apologies for the late response. Engineering team doesn't recommend transferring the clock signal as the uncertainty on the clock path will be too high to reasonably close timing. It is better to just send a delay matched clock to each die.
Can you confirm- are you trying to have one clock source in one die and have the signal transferred to the other die?
If you were to refer to the example design generated in IP catalog/Platform Designer, you'll be able to see the constraint values used for DIB IP. However these constraints are for 50MHz operation. From your project I can't tell what speed you intend the DIB IP to run on.
Regards,
Nurina
Occasional ContributorHi Nurina,
1. the clock is 13.3Mhz .
2. what is "delay matched clock to each die." ? - send same clock to both dies , but what is the meaning of delay ?
3. Yes I'm trying to have one Clock Source in Die 0 , and transfer the data along with the clock via the DIB to the other Die.
4. even we move to "System Synchronous" (I guess this is what you suggest in "Delay Matched Clock" I'm still looking for the values - see item 3 at my post at "01-03-2023 03:54 AM"
BTW it is not written in any document that DIB does not support Clock Transfer via DIB - and now we need to do Huge change in my design - I recommend that Intel will comment about that .
in addition , can you tell if I need to define special parameters when I generate example design ? where can I find the constraints of the 50Mhz you wrote above ?
Or.
