Forum Discussion

OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Stratix 10M DIB Module

Hi I'm using the DIB to inter connect between the 2 dies of the Stratix 10 I'm using it in BYPASS (therefore I need to define the constraints) mode and one of the IO is transferring clock from ...
  • Nurina's avatar
    Nurina
    3 years ago

    Hi,


    I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.

    You can start with the values they put for the example design and fine tune it after compilation.

    Below are the values used:

    • max C=2.65
    • min C=-2.65
    • max A + max B = 8.25
    • min A + min B = 3
    • max D + max E = 4.75
    • min D + min E = -1.64


    Regards,

    Nurina


  • OrF's avatar
    OrF
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    I'm aware of this document ,

    The document leaves many open questions , and does not refer to my questions.

    1. The document is talking about system synchronous and not Source synchronous as my case.
    2. I didn't find any place that specifies the values of B,C,D Timing values (at the Figure 16) the only timing which was specifies is 2.5ns, it is not written if 2.5ns = EMIB Delay (C values) , or the DIB Latency (B,D values) - or all the values together .
    3. My question was to where should I set the input/output delays practically in the SDC, which means to which pins or ports?, it is not written in the document , what is the dib_0 module (in my original question) stand for , is it the "Die B DIB" (at figure 16)? or it is " EMIB+DIE B DIB " ?
    4. The importance of item 3 above is to understand if quartos timing analyzer , takes into account the internal routing of dib_0 and derived the clock definition in the input side and add the Routing delay inside the dib_0 module

    Thanks

    Or