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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Stratix 10M DIB Module

Hi I'm using the DIB to inter connect between the 2 dies of the Stratix 10 I'm using it in BYPASS (therefore I need to define the constraints) mode and one of the IO is transferring clock from ...
  • Nurina's avatar
    Nurina
    3 years ago

    Hi,


    I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.

    You can start with the values they put for the example design and fine tune it after compilation.

    Below are the values used:

    • max C=2.65
    • min C=-2.65
    • max A + max B = 8.25
    • min A + min B = 3
    • max D + max E = 4.75
    • min D + min E = -1.64


    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Or,


In Bypass mode, there is no clock transfer involved. In bypass mode, this IP essentially acts as a wire between 2 dies with one reference clock, so it isn't system synchronous. In figure 16 of the following document, you can see that there is an IOPLL in both dies, implying that this is also a source synchronous design https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html


How are you using the DIB IP? Are you sure you should be using bypass mode, not synchronous mode?


In figure 16 of the above document, you can see that the EMIB delay is the propagation delay between two dies. It is mentioned in this document that it's the wire delay https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/bypass-mode.html


I don't have access to the slides, I'm not sure if you can share a snapshot here either.


Can you share your project so I can understand how you are using it?


Thanks,

Nurina


  • OrF's avatar
    OrF
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Nurina.

    1. the course / Slides are intel's course how come you dont have access to something that intel publish .

    do you have access to this web page :

    https://learning.intel.com/Developer/pages/30/all-intel-developer-training

    then search :"constraining source synchronous (E-Learning) " and see the course

    this course will explain you what is source synchronous and the constraints you need to assign (in general not on DIB specifically )

    in addition you can read the document from Intel - attached it now since somehow you can not load it .

    I recommend that you do the course first .

    2. I'm using ByPass mode of DIB - which means using the DIB as "cable connection" or "replacing cable" , on the DIB you can transfer data , but you can also transfer clock along the data - not as points to the document which is synchronous design . (please watch the course or read what is source synchronous ) . when you transfer clock you have different constraints you need to assign for the input and output delay.

    3. Regarding the delay. you are confusing me in your answer .

    at your first answer Quotation "The B,C,D timing values from Figure 16 of the above document is as follows. B=D=DIB Latency=2.5ns as mentioned here https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html. EMIB Delay=C=Wire Delay of Stratix 10"

    B, D are 2.5 ns DIB Latency what was missing is the EMIB Delay(C , Wire Delay) , and then in your last answer , you sent me to a document which is again talking about DIB Latency and NOT EMIB Delay ...

    Quotation from the Document .... "The latency between DIB pins is 2.5 ns."

    so Intel Document is missing the finial numbers of DIB Latency and EMIB Delay ... what is the total delay B+C+D = 7.5ns / B+C =5ns or just C=5ns ...

    even if working with system Synconus as in the example here: https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html

    you need the Value B , C , D which are not described in the document ... (there only vouge number 2.5ns from the document quotation "The latency between DIB pins is 2.5 ns." which is not understood to what parameter it is set .