Forum Discussion
Occasional ContributorStratix 10M DIB Module
Hi,
I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.
You can start with the values they put for the example design and fine tune it after compilation.
Below are the values used:
- max C=2.65
- min C=-2.65
- max A + max B = 8.25
- min A + min B = 3
- max D + max E = 4.75
- min D + min E = -1.64
Regards,
Nurina
Regular ContributorHi Or,
In Bypass mode, there is no clock transfer involved. In bypass mode, this IP essentially acts as a wire between 2 dies with one reference clock, so it isn't system synchronous. In figure 16 of the following document, you can see that there is an IOPLL in both dies, implying that this is also a source synchronous design https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html
How are you using the DIB IP? Are you sure you should be using bypass mode, not synchronous mode?
In figure 16 of the above document, you can see that the EMIB delay is the propagation delay between two dies. It is mentioned in this document that it's the wire delay https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/bypass-mode.html
I don't have access to the slides, I'm not sure if you can share a snapshot here either.
Can you share your project so I can understand how you are using it?
Thanks,
Nurina
