DE1-SoC project compiles, but board programming fails 42% through

Hello,

When programming the board reaches 42%, I get the following error:

Info (209017): Device 2 contains JTAG ID code 0x02D120DD

Error (209040): Can't access JTAG chain

Error (209015): Can't configure device. Expected JTAG ID code 0x02D120DD for device 2, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).

 I manage to program it with other designs, so it shouldn't be a physical problem.

This is considering a fairly basic project. Here's the platform designer layout:

Files in the project are only:

1. The auto generated .qip file,
2.  And a top module:

module DE1_SoC_Computer (

ports list);

declarations

// From Qsys

Computer_System The_System (

.sys_sdram_pll_0_ref_clk_clk (CLOCK_50),

.sys_sdram_pll_0_ref_reset_reset (KEY[0]),

.sys_sdram_pll_0_sdram_clk_clk (DRAM_CLK),

.new_sdram_controller_0_wire_addr (DRAM_ADDR), // new_sdram_controller_0_wire.addr

.new_sdram_controller_0_wire_ba (DRAM_BA), // .ba

.new_sdram_controller_0_wire_cas_n (DRAM_CAS_N), // .cas_n

.new_sdram_controller_0_wire_cke (DRAM_CKE), // .cke

.new_sdram_controller_0_wire_cs_n (DRAM_CS_N), // .cs_n

.new_sdram_controller_0_wire_dq (DRAM_DQ), // .dq

.new_sdram_controller_0_wire_dqm ({DRAM_UDQM,DRAM_LDQM}), 

.new_sdram_controller_0_wire_ras_n (DRAM_RAS_N), // .ras_n

.new_sdram_controller_0_wire_we_n (DRAM_WE_N), // .we_n

.fifo_0_out_valid (fifo_valid), // fifo_0_out.valid

.fifo_0_out_data (fifo_data), // .data

.fifo_0_out_ready (fifo_ready), // .ready

.fifo_0_out_channel (), // .channel

.fifo_0_out_error (), // .error

.fifo_0_out_startofpacket (fifo_sop), // .startofpacket

.fifo_0_out_endofpacket (fifo_eop), // .endofpacket

.fifo_0_out_empty (fifo_empty), // .empty

.mm_bridge_0_s0_waitrequest (mm_waitrequest), // mm_bridge_0_s0.waitrequest

.mm_bridge_0_s0_readdata (mm_readdata), // .readdata

.mm_bridge_0_s0_readdatavalid (mm_readdatavalid), // .readdatavalid

.mm_bridge_0_s0_burstcount (mm_burstcount), // .burstcount

.mm_bridge_0_s0_writedata (mm_writedata), // .writedata

.mm_bridge_0_s0_address (mm_address), // .address

.mm_bridge_0_s0_write (mm_write), // .write

.mm_bridge_0_s0_read (mm_read), // .read

.mm_bridge_0_s0_byteenable (mm_byteenable), // .byteenable

.mm_bridge_0_s0_debugaccess (mm_debugaccess), // .debugaccess

// HPS DDR3

.hps_0_ddr_mem_a (HPS_DDR3_ADDR),

.hps_0_ddr_mem_ba (HPS_DDR3_BA),

.hps_0_ddr_mem_ck (HPS_DDR3_CK_P),

.hps_0_ddr_mem_ck_n (HPS_DDR3_CK_N),

.hps_0_ddr_mem_cke (HPS_DDR3_CKE),

.hps_0_ddr_mem_cs_n (HPS_DDR3_CS_N),

.hps_0_ddr_mem_ras_n (HPS_DDR3_RAS_N),

.hps_0_ddr_mem_cas_n (HPS_DDR3_CAS_N),

.hps_0_ddr_mem_we_n (HPS_DDR3_WE_N),

.hps_0_ddr_mem_reset_n (HPS_DDR3_RESET_N),

.hps_0_ddr_mem_dq (HPS_DDR3_DQ),

.hps_0_ddr_mem_dqs (HPS_DDR3_DQS_P),

.hps_0_ddr_mem_dqs_n (HPS_DDR3_DQS_N),

.hps_0_ddr_mem_odt (HPS_DDR3_ODT),

.hps_0_ddr_mem_dm (HPS_DDR3_DM),

.hps_0_ddr_oct_rzqin (HPS_DDR3_RZQ),

// HPS Peripherals (Ethernet, USB, etc.)

.hps_0_hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),

.hps_0_hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),

.hps_0_hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),

.hps_0_hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),

.hps_0_hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),

.hps_0_hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),

.hps_0_hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),

.hps_0_hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),

.hps_0_hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),

.hps_0_hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),

.hps_0_hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),

.hps_0_hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),

.hps_0_hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),

.hps_0_hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),

.hps_0_hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),

.hps_0_hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),

.hps_0_hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),

.hps_0_hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),

.hps_0_hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),

.hps_0_hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),

.hps_0_hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),

.hps_0_hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),

.hps_0_hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),

.hps_0_hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),

.hps_0_hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),

.hps_0_hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),

.hps_0_hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),

.hps_0_hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),

.hps_0_hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),

.hps_0_hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),

.hps_0_hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),

.hps_0_hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),

.hps_0_hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),

.hps_0_hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),

.hps_0_hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),

.hps_0_hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),

.hps_0_hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),

.hps_0_hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT),

.hps_0_hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),

.hps_0_hps_io_hps_io_uart0_inst_TX (HPS_UART_TX)

);

multi_tile_solver solver_inst (

.clock (CLOCK_50),

.reset (KEY[0]),

.in_data (fifo_data),

.in_valid (fifo_valid),

.in_end_of_stream (fifo_eop),

.in_ready (fifo_ready),

.out_data (mm_writedata),

.out_addr (mm_address), // The solver keeps its full 32-bit view

.out_write_en (mm_write),

.out_ack (solver_ack)

);

endmodule // end top level

The Platform Designer auto-generated Comuter_System.v has the ports list:

module Computer_System (

output wire fifo_0_out_valid, // fifo_0_out.valid

output wire [31:0] fifo_0_out_data, // .data

output wire [7:0] fifo_0_out_channel, // .channel

output wire [7:0] fifo_0_out_error, // .error

output wire fifo_0_out_startofpacket, // .startofpacket

output wire fifo_0_out_endofpacket, // .endofpacket

output wire [1:0] fifo_0_out_empty, // .empty

input wire fifo_0_out_ready, // .ready

output wire [12:0] hps_0_ddr_mem_a, // hps_0_ddr.mem_a

output wire [2:0] hps_0_ddr_mem_ba, // .mem_ba

output wire hps_0_ddr_mem_ck, // .mem_ck

output wire hps_0_ddr_mem_ck_n, // .mem_ck_n

output wire hps_0_ddr_mem_cke, // .mem_cke

output wire hps_0_ddr_mem_cs_n, // .mem_cs_n

output wire hps_0_ddr_mem_ras_n, // .mem_ras_n

output wire hps_0_ddr_mem_cas_n, // .mem_cas_n

output wire hps_0_ddr_mem_we_n, // .mem_we_n

output wire hps_0_ddr_mem_reset_n, // .mem_reset_n

inout wire [7:0] hps_0_ddr_mem_dq, // .mem_dq

inout wire hps_0_ddr_mem_dqs, // .mem_dqs

inout wire hps_0_ddr_mem_dqs_n, // .mem_dqs_n

output wire hps_0_ddr_mem_odt, // .mem_odt

output wire hps_0_ddr_mem_dm, // .mem_dm

input wire hps_0_ddr_oct_rzqin, // .oct_rzqin

output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK

output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0

output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1

output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2

output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3

input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0

inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO

output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC

input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL

output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL

input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK

input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1

input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2

input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3

inout wire hps_0_hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0

inout wire hps_0_hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1

inout wire hps_0_hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2

inout wire hps_0_hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3

output wire hps_0_hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0

output wire hps_0_hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK

inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD

inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0

inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1

output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK

inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2

inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3

inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0

inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1

inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2

inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3

inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4

inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5

inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6

inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7

input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK

output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP

input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR

input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT

input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX

output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX

output wire mm_bridge_0_s0_waitrequest, // mm_bridge_0_s0.waitrequest

output wire [15:0] mm_bridge_0_s0_readdata, // .readdata

output wire mm_bridge_0_s0_readdatavalid, // .readdatavalid

input wire [0:0] mm_bridge_0_s0_burstcount, // .burstcount

input wire [15:0] mm_bridge_0_s0_writedata, // .writedata

input wire [31:0] mm_bridge_0_s0_address, // .address

input wire mm_bridge_0_s0_write, // .write

input wire mm_bridge_0_s0_read, // .read

input wire [1:0] mm_bridge_0_s0_byteenable, // .byteenable

input wire mm_bridge_0_s0_debugaccess, // .debugaccess

output wire [12:0] new_sdram_controller_0_wire_addr, // new_sdram_controller_0_wire.addr

output wire [1:0] new_sdram_controller_0_wire_ba, // .ba

output wire new_sdram_controller_0_wire_cas_n, // .cas_n

output wire new_sdram_controller_0_wire_cke, // .cke

output wire new_sdram_controller_0_wire_cs_n, // .cs_n

inout wire [15:0] new_sdram_controller_0_wire_dq, // .dq

output wire [1:0] new_sdram_controller_0_wire_dqm, // .dqm

output wire new_sdram_controller_0_wire_ras_n, // .ras_n

output wire new_sdram_controller_0_wire_we_n, // .we_n

input wire sys_sdram_pll_0_ref_clk_clk, // sys_sdram_pll_0_ref_clk.clk

input wire sys_sdram_pll_0_ref_reset_reset, // sys_sdram_pll_0_ref_reset.reset

output wire sys_sdram_pll_0_sdram_clk_clk // sys_sdram_pll_0_sdram_clk.clk

);
...

What is causing this failure?