Occasional ContributorStratix 10M DIB Module
Hi
I'm using the DIB to inter connect between the 2 dies of the Stratix 10
I'm using it in BYPASS (therefore I need to define the constraints) mode and one of the IO is transferring clock from one side to another - source synchronous.
I generated DIB Module from the IP catalog (dib_rx_altera_dib_1930_u7lqq6i)
at the synthesis / fitter stage I would like to assign the constraints to the IO
the question is to where should I assign / define the Clock in the constraints , and the input delay ?
to DIE1_dib_pad_2_22_2[18] or to OUT[18] (in the case of the Clock) , and similar to the input delay ?
if I will assign Input Side DIE1_dib_pad_2_22_2[18] - will quartos/ timing analyzer will understand that OUT[18] is a clock (and take into account the routing delay) ?
or the dib_0 module is Blackbox for the timing analyzer and I should define the clock and IO input delays on the OUT[18] ?
my understanding that the input from the EMIB inserted to the Die1 via DIE1_dib_pad_2_22_2[18] , dib_0 module does nothing in bypass mode (just routing) , and the OUT[18] is the continuation of the wire .
thanks
Or.
Hi,
I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.
You can start with the values they put for the example design and fine tune it after compilation.
Below are the values used:
- max C=2.65
- min C=-2.65
- max A + max B = 8.25
- min A + min B = 3
- max D + max E = 4.75
- min D + min E = -1.64
Regards,
Nurina
