Forum Discussion
Occasional ContributorStratix 10M DIB Module
Hi,
I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.
You can start with the values they put for the example design and fine tune it after compilation.
Below are the values used:
- max C=2.65
- min C=-2.65
- max A + max B = 8.25
- min A + min B = 3
- max D + max E = 4.75
- min D + min E = -1.64
Regards,
Nurina
Regular ContributorHello Or,
What I mean by delay matched clock is that the clock hitting the clock pin of each die is matched. Best way to do that is to have a clock gen on your board with two matched outputs and route those signals to each die with matched trace lengths. That ensures that each FPGA has a clock coming in that's matched.
In this case you wouldn't need the DIB IP at all.
It is possible to send a clock over from one die to another using DIB IP, but due to high clock uncertainty, it will be very difficult to ensure the proper timing constraints and addressing any potential CDC. There is a high chance of hardware failure which is why I'm suggesting against sending a clock over through DIB IP.
To generate the example design, go to Project>Upgrade IP Components and double click on the DIB IP and Quartus will open IP Parameter Editor. At the toolbar go to Generate>Generate Example Design. Once generating the example design, you can run a compilation and take a look at the SDC file in the example design. The example design will use 50MHz clock by default.
Regards,
Nurina
OrFHi
regarding your comment : "In this case you wouldn't need the DIB IP at all."
- if I get you right , you mean that I don't need DIB IP for sending clock from die to die ?
, but I do need DIB IP for transferring data from Die to Die (I dont see other way to transfer data )
Or.
