Honored ContributorHi all
I'm using a PLL on a cyclone III device to generate an 12.228 MHz clock from a 19.2 MHz input. the output clock is a square wave which causes harmonics that interferes with an RF application. I tries the minimum current setting but it didn't canceled the high harmonics. is there a way to configure the output clock as a sine wave? thanks in advance
Honored ContributorUse an external LC filter.
Honored ContributorThanks for the quick replay, but I'm looking for a solution inside the FPGA, since I don't want to reedit the board.
Honored Contributoryou can not create analog output by cycloneIII.
Honored ContributorDid you try setting minimum slew rate for the output?
Maybe this will reduce some high frequency harmonics. You can also add a single capacitor to the output to obtain a more triangular wavwform.Honored ContributorHi
I tried the minimum current setting. as I understand it, this setting is equivalent to the minimum slew rate setting.Honored ContributorHonored ContributorYou could additionally specify 50 ohms series termination for the output signal. I do that for any output (or bidir) signal if possible , i.e. for any point-to-point connection.
Honored Contributorwhen I tried adding a series resistor without calibration to 3.3V LVTTL I've received an error message, I only managed it with 3.0V standard.
using the series resistor with calibration will require another round of board editing...Honored Contributor
