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Honored Contributor
Honored Contributorsmoothing PLL output
Hi all I'm using a PLL on a cyclone III device to generate an 12.228 MHz clock from a 19.2 MHz input. the output clock is a square wave which causes harmonics that interferes with an RF appli...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I tried the minimum current setting. as I understand it, this setting is equivalent to the minimum slew rate setting. --- Quote End --- Slow slew rate is a feature of the output pre-driver available with some FPGA families, while current strength is an output feature. But none of them will have considerable effect in the frequency range you are looking for. That's why I suggested an external filter. The parallel capacitor suggested by nplttr is all you can achieve without changing the board.
