Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

smoothing PLL output

Hi all I'm using a PLL on a cyclone III device to generate an 12.228 MHz clock from a 19.2 MHz input. the output clock is a square wave which causes harmonics that interferes with an RF appli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Slow slew rate is a feature of the output pre-driver available with some FPGA families, while current strength is an output feature. But none of them will have considerable effect in the frequency range you are looking for. That's why I suggested an external filter. The parallel capacitor suggested by nplttr is all you can achieve without changing the board.

--- Quote End ---

can you please elaborate on the difference? I've always wondered why they have tow identical assignments, now I understand they are not identical...