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Altera_Forum
Honored Contributor
15 years agosmoothing PLL output
Hi all I'm using a PLL on a cyclone III device to generate an 12.228 MHz clock from a 19.2 MHz input. the output clock is a square wave which causes harmonics that interferes with an RF appli...
Altera_Forum
Honored Contributor
15 years agoThanks for the quick replay, but I'm looking for a solution inside the FPGA, since I don't want to reedit the board.