simple verilog question...

thanks for the response Kaz!

Let me break it down a bit more however. The two expressions are actually the same (logically). But the outcome is different. In other words,

assign X_n = ~X;

always@(posedge CLK)

begin

Y = X_n * 625;

end

DOES NOT equal the below equation

always@(posedge CLK)

begin

Y = ~X * 625;

end

--- Quote Start ---

thanks for the response Kaz!

Let me break it down a bit more however. The two expressions are actually the same (logically). But the outcome is different. In other words,

assign X_n = ~X;

always@(posedge CLK)

begin

Y = X_n * 625;

end

DOES NOT equal the below equation

always@(posedge CLK)

begin

Y = ~X * 625;

end

--- Quote End ---

I deleted my initial post because it turned out unrelated !!

you started presenting your problem as 2's complement conversion ...But the issue is actually about two apparently equivalent expressions having two results.

What I supposed first was this:

unsigned to signed: invert bits then add 1

signed to unsigned :subtract 1 then invert bits = invert bits then add 1

clearly irrelevant but the order of operations is important.

Regarding your issue, I suggest you post your entire code.

Im also think there is somthing involved in your data types.

Can you show a snipset of the code with the data types and width included?

Here is the code in question...

--- Quote Start ---

input [11:0] input_temp;

output [7:0] actual_temp; //actual temperature

reg [21:0] temp;

wire [10:0] input_temp_n;

assign actual_temp = temp/10000;

assign input_temp_n = (~input_temp[10:0]) + 1;

always@(posedge iCLK)

begin

if(!input_temp[11])

begin

temp = (input_temp[10:0] * 625);

end

else

begin

temp = (input_temp_n * 625);

//offending code

//temp = ((~input_temp[10:0] + 1) * 625);

end

end

--- Quote End ---

BTW sorry for lack of indentation. i dont know why but these forums kill my indentation. anyone know how to fix?

Hi,

I had a quick go at your code and reproduced your finding.

Your design is not constrained in the sense of data bitwidth into and out of operations.

in the first expression, your multiplier gives correct output.

in the second expression, your multiplier gives correct output for 11 bits only, other bits are set by compiler to wrong values, apparently considered as don't care.

I also notice that you are keeping positive input values but forcing negative input values to positive. Is that what you really intend to do?

I suggest you declare signed types for inputs and outputs and constrain the width of all your results at all stages.