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Altera_Forum's avatar
Altera_Forum
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15 years ago

simple verilog question...

hi there! im trying to determine the root cause of an error i keep getting. Basically I'm trying to convert a 2's complement value, lets say binary X to decimal Y (i do this by multiplying...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I already mentioned, that the intermediate result bitwidth causes a different result. Thus I had been asking for the definition of data types used in the original example, but we face considerably different Verilog text in each post. Consequently, the results are different for each example. I miss a clear question now.