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Altera_Forum
Honored Contributor
Honored Contributorsimple verilog question...
hi there! im trying to determine the root cause of an error i keep getting. Basically I'm trying to convert a 2's complement value, lets say binary X to decimal Y (i do this by multiplying...
Altera_ForumHonored Contributor
Honored ContributorI already mentioned, that the intermediate result bitwidth causes a different result. Thus I had been asking for the definition of data types used in the original example, but we face considerably different Verilog text in each post. Consequently, the results are different for each example. I miss a clear question now.
