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Altera_Forum's avatar
Altera_Forum
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15 years ago

simple verilog question...

hi there! im trying to determine the root cause of an error i keep getting. Basically I'm trying to convert a 2's complement value, lets say binary X to decimal Y (i do this by multiplying...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Seriously, we can't know what's the expectable or correct result without knowing the involved data types. Bit width of signals is most likely the key to understand why the results are different. When assinging X_n = ~X - 1, the result is truncated to a specified width. In Y = (~X - 1) * 625, the intermediate result gets a default width of 32 bit.