simple verilog question...

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thanks for the response Kaz!

Let me break it down a bit more however. The two expressions are actually the same (logically). But the outcome is different. In other words,

assign X_n = ~X;

always@(posedge CLK)

begin

Y = X_n * 625;

end

DOES NOT equal the below equation

always@(posedge CLK)

begin

Y = ~X * 625;

end

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I deleted my initial post because it turned out unrelated !!

you started presenting your problem as 2's complement conversion ...But the issue is actually about two apparently equivalent expressions having two results.

What I supposed first was this:

unsigned to signed: invert bits then add 1

signed to unsigned :subtract 1 then invert bits = invert bits then add 1

clearly irrelevant but the order of operations is important.

Regarding your issue, I suggest you post your entire code.