simple verilog question...

Hi,

I had a quick go at your code and reproduced your finding.

Your design is not constrained in the sense of data bitwidth into and out of operations.

in the first expression, your multiplier gives correct output.

in the second expression, your multiplier gives correct output for 11 bits only, other bits are set by compiler to wrong values, apparently considered as don't care.

I also notice that you are keeping positive input values but forcing negative input values to positive. Is that what you really intend to do?

I suggest you declare signed types for inputs and outputs and constrain the width of all your results at all stages.