simple verilog question...

Here is the code in question...

--- Quote Start ---

input [11:0] input_temp;

output [7:0] actual_temp; //actual temperature

reg [21:0] temp;

wire [10:0] input_temp_n;

assign actual_temp = temp/10000;

assign input_temp_n = (~input_temp[10:0]) + 1;

always@(posedge iCLK)

begin

if(!input_temp[11])

begin

temp = (input_temp[10:0] * 625);

end

else

begin

temp = (input_temp_n * 625);

//offending code

//temp = ((~input_temp[10:0] + 1) * 625);

end

end

--- Quote End ---

BTW sorry for lack of indentation. i dont know why but these forums kill my indentation. anyone know how to fix?