SignalTap different sample depth led to different logic

Does your design meet timing? 'Simply' doubling the RAM size may have ramifications on fit and timing. Make sure it meets timing.

Cheers,

Alex

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Does your design meet timing? 'Simply' doubling the RAM size may have ramifications on fit and timing. Make sure it meets timing.

Cheers,

Alex

--- Quote End ---

Thank you Alex.

I only have some unconstrained paths:

+---------------------------------------------------+

; Unconstrained Paths ;

+-------------------------------------+-------+-------+

; Property ; Setup ; Hold ;

+-------------------------------------+-------+-------+

; Illegal Clocks ; 0 ; 0 ;

; Unconstrained Clocks ; 2 ; 2 ;

; Unconstrained Input Ports ; 3 ; 3 ;

; Unconstrained Input Port Paths ; 188 ; 188 ;

; Unconstrained Output Ports ; 33 ; 33 ;

; Unconstrained Output Port Paths ; 16901 ; 16901 ;

+---------------------------------+-------+-------+

Could this be the problem?

Thank you.

Leon

it depends if they are critical to the design you are checking.

Do you also have some asynchronous paths into the logic?

Did you check that the design met timing?

--- Quote Start ---

it depends if they are critical to the design you are checking.

Do you also have some asynchronous paths into the logic?

Did you check that the design met timing?

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Hi Tricky,

Yes I have asynchronous paths in the logic.

The timing is OK since the TimeQuest Timing Analysis is green and nike after compile design. The only timing related issues are some Unconstrained Paths shown above.

Thank you!

Leon

Asynchronous paths are also an issue. They will not be timed, and their path delay will vary from build to build and with temperature.

Make sure everything is synchronised and everything is constrained.

Thank you guys. The problem is solved after adding some timing constraints to the clocks lol.

Leon