SignalTap different sample depth led to different logic

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Does your design meet timing? 'Simply' doubling the RAM size may have ramifications on fit and timing. Make sure it meets timing.

Cheers,

Alex

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Thank you Alex.

I only have some unconstrained paths:

+---------------------------------------------------+

; Unconstrained Paths ;

+-------------------------------------+-------+-------+

; Property ; Setup ; Hold ;

+-------------------------------------+-------+-------+

; Illegal Clocks ; 0 ; 0 ;

; Unconstrained Clocks ; 2 ; 2 ;

; Unconstrained Input Ports ; 3 ; 3 ;

; Unconstrained Input Port Paths ; 188 ; 188 ;

; Unconstrained Output Ports ; 33 ; 33 ;

; Unconstrained Output Port Paths ; 16901 ; 16901 ;

+---------------------------------+-------+-------+

Could this be the problem?

Thank you.

Leon