Honored ContributorHi,
I am a newbie to Altera CPLD. I have a signal A and it's compliment signal B. I would want signal B to always lag 1us w.r.t signal A at the rising edge. And signal A lags signal B by 1us at the falling edge of signal A. So that signal B's pulse width is 2us shorter than signal A's pulse width (1us at each edge). Thanks.
Honored ContributorTo accomplish this, signal A must be periodic (or should follow a known pattern). i.e. you have to know when the falling edge of A will happen in advance. If signal A is not periodic, you cannot predict when it will fall and therefore you cannot make B fall before A falls.
In addition to this, you will need a clock so you can sample signal A.Honored ContributorI'm assuming the waveforms look like this
________________
A: ___| |____
________
B: _______| |_________
I think that if these signals are what are required then a simple state machine would do the job. There are four regions. S1 is A high and B low, S2 is A and B high, and S3 is A high and B low. Obviously the "B" signal would be inverted from this for the final output. S0 is idle state. -James
Honored ContributorThanks for the replies.
@ Kosh271 You have got the timing diagram right. signals A and B are generated by CPLD, hence they are outputs. A is dependent on an external event which is periodic most of the time. I can use a fixed pulse width for A. Tolerance on B can be +/- 10ns. RT and FT time <=15ns. I do have a external clock into CPLD of 4.6MHz.Honored Contributorif my pulse width is 100us I think I can do the following:
Detect Rising edge of A using D latch and inverter. (any tips?) wait for 1us generate signal B = Not A wait for 98us Invert B The above sequence will only be true if A's pulse width is known.Honored ContributorEddie13 - It sounds like you have the basics worked out.
I'm not entirely sure if you will be able to meet your timing tolerance with your input clock. The clock period is ~217.4 nS, so I would think that even reaching your goal of 1 uS could be difficult. If A is run thru a register (D-flip flop), you could be roughly 90 nS late on the rising edge. The falling edge (at 99 uS after the rising edge of A) works out quite well lands at a nice even multiple of your clock.Honored ContributorIt will hardly work without a FPGA and PLL clock multiply. I presume you know that "wait xx us" implies counting clock cycles.
You don't clearly distinguish between the timing of the "external event" and signal A, although you say signal A is an output of the CPLD. So it's not the same as the external event? If the external event is unrelated to the 4.6 MHz clock (the general case), synchronization jitter must be considered. There's no specification yet.
